Modern electronics, such as smart phones, personal digital assistants, location based services devices, and enterprise class appliances, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. As more functions are packed into the integrated circuits and more integrated circuits into the package, integrated circuit packages must continue to provide a mechanism for making electrical interconnection between the integrated circuit die and the leads that are utilized to make electrical interconnections to circuits, power, and ground external to the integrated circuit die. In the early stages of integrated circuit development, there were relatively few connections between the integrated circuit die and the external circuitry.
For those early types of integrated circuits, the interconnection to the integrated circuit package was relatively straightforward and generally involved leads arranged around a die cavity to be electrically connected to die pads. There were also relatively few circuits on each integrated circuit die and the circuit operational rates were, by modern day standards, relatively slow. Accordingly, the spacing and configuration of the leads with respect to the die pads did not pose additional difficulty for reliable assembly.
Virtually across all applications, there continues to be growing demand for reducing size of the integrated circuits. However, the size reduction often does not come with input/output (I/O) reduction for the integrated circuit to communicate to the external circuitry. As the integrated circuit technology advanced, more circuitry were able to be fabricated in a similar die area so that substantially increased functionality could be accomplished on a given integrated circuit die. The added functionality and increase in the number of circuitry involved generally required a larger number of discrete connections to the external world. As physical sizes decreased and the number of required die pads increased, it was necessary to develop integrated circuit dice and packages that would accommodate connections to a larger number of external connections. Both integrated circuit developers and integrated package manufacturers worked to develop die interconnect systems that would accommodate the higher die pad densities.
Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the mature technologies. Research and development in the existing technologies may take a myriad of different directions. These approaches may involve improving integrated circuit technology, package technology, or a combination thereof.
The design process for integrated circuits usually consists of parallel design of the core circuitry and the I/O cell circuitry with a subsequent integration of the two. The I/O cell circuitry is usually developed in the form of “cell libraries” from which the desired cells for a given integrated circuit design are invoked, “dropped in” and wired to the core circuitry with suitable place and route tools.
The I/O cell circuitry, which consists of functional elements such as I/O drivers, electrostatic discharge (ESD) structures, and the bonding pads for external connection to a package, is usually contained within an “I/O cell”. The appropriate I/O cells are then instantiated around the core of the chip by the chip design tools. The pitch of the I/O cells, and thus the pitch of the bonding pads, is an important parameter from the packaging standpoint.
For I/O intensive designs, the pitch is very fine (˜50 um or less), making the packaging task more difficult. As such, so-called “staggered designs” have been developed, wherein I/O cells at alternating locations are offset relative to their nearest neighbors, resulting in a greater direct distance between adjacent bonding pads, thereby somewhat alleviating the task of packaging the chip.
Unfortunately, this approach also results in a die size penalty approximately equal to two times the amount of die pad offset per side. The die size penalty results in correspondingly fewer die per wafer and higher unit cost per die, which is understandably undesirable.
Thus, a need still remains for an integrated circuit package system having improved I/O cells providing reduced die size and providing higher I/O count without placing undesired burden on the packaging process. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.